module OH_MPI (
   RESET,

  // interface to global CPU interface
   CPU_CLK,
   CPU_CS,
   CPU_WREN,
   CPU_ADDR,
   CPU_WDATA,
   CPU_RDATA,

  // registers bus control the POH insert
   MPI_TPOH_J1,
   MPI_TPOH_C2,
   MPI_TPOH_G1,
   MPI_TPOH_F2,
   MPI_TPOH_H4,
   MPI_TPOH_F3,
   MPI_TPOH_K2,
   MPI_TPOH_N1,
  // registers for HDLC interface control
   MPI_HDLC_LATENCY
   );

input                 RESET;

input                 CPU_CLK;
input                 CPU_CS;
input                 CPU_WREN;
input[7:0]            CPU_ADDR;
input[15:0]           CPU_WDATA;
output reg[15:0]      CPU_RDATA;

output reg[511:0]     MPI_TPOH_J1;
output reg[7:0]       MPI_TPOH_C2;
output reg[7:0]       MPI_TPOH_G1;
output reg[7:0]       MPI_TPOH_F2;
output reg[7:0]       MPI_TPOH_H4;
output reg[7:0]       MPI_TPOH_F3;
output reg[7:0]       MPI_TPOH_K2;
output reg[7:0]       MPI_TPOH_N1;

output reg[3:0]       MPI_HDLC_LATENCY;


//******* POH Registers MAP   ********//
//0xB2  BIT7-BIT0     Tx-C2
//0xB3  BIT7-BIT0     Tx-G1
//0xB4  BIT7-BIT0     Tx-F2
//0xB4  BIT7-BIT0     Tx-H4
//0xB4  BIT7-BIT0     Tx-F3
//0xB4  BIT7-BIT0     Tx-K2
//0xB4  BIT7-BIT0     Tx-N1
//0xE0-0xFF    BIT15-BIT0       Tx-J1


always @(posedge RESET or posedge CPU_CLK) begin
   if ( RESET==1'b1 ) begin
      MPI_TPOH_J1[511:0]            <= 512'd0;
      MPI_TPOH_C2[7:0]              <= 8'd0;
      MPI_TPOH_G1[7:0]              <= 8'd0;
      MPI_TPOH_F2[7:0]              <= 8'd0;
      MPI_TPOH_H4[7:0]              <= 8'd0;
      MPI_TPOH_F3[7:0]              <= 8'd0;
      MPI_TPOH_K2[7:0]              <= 8'd0;
      MPI_TPOH_N1[7:0]              <= 8'd0;
      MPI_HDLC_LATENCY[3:0]         <= 4'd0;
   end
   else if ( CPU_CS==1'b1 && CPU_WREN==1'b1 ) begin
      case ( CPU_ADDR[7:0] )
      8'hB2:  MPI_TPOH_C2[7:0]      <= CPU_WDATA[7:0];
      8'hB3:  MPI_TPOH_G1[7:0]      <= CPU_WDATA[7:0];
      8'hB4:  MPI_TPOH_F2[7:0]      <= CPU_WDATA[7:0];
      8'hB5:  MPI_TPOH_H4[7:0]      <= CPU_WDATA[7:0];
      8'hB6:  MPI_TPOH_F3[7:0]      <= CPU_WDATA[7:0];
      8'hB7:  MPI_TPOH_K2[7:0]      <= CPU_WDATA[7:0];
      8'hB8:  MPI_TPOH_N1[7:0]      <= CPU_WDATA[7:0];
      8'hBC:  MPI_HDLC_LATENCY[3:0] <= CPU_WDATA[3:0];

      8'hE0:  MPI_TPOH_J1[16*0+15 : 16*0]        <= CPU_WDATA[15:0];
      8'hE1:  MPI_TPOH_J1[16*1+15 : 16*1]        <= CPU_WDATA[15:0];
      8'hE2:  MPI_TPOH_J1[16*2+15 : 16*2]        <= CPU_WDATA[15:0];
      8'hE3:  MPI_TPOH_J1[16*3+15 : 16*3]        <= CPU_WDATA[15:0];
      8'hE4:  MPI_TPOH_J1[16*4+15 : 16*4]        <= CPU_WDATA[15:0];
      8'hE5:  MPI_TPOH_J1[16*5+15 : 16*5]        <= CPU_WDATA[15:0];
      8'hE6:  MPI_TPOH_J1[16*6+15 : 16*6]        <= CPU_WDATA[15:0];
      8'hE7:  MPI_TPOH_J1[16*7+15 : 16*7]        <= CPU_WDATA[15:0];
      8'hE8:  MPI_TPOH_J1[16*8+15 : 16*8]        <= CPU_WDATA[15:0];
      8'hE9:  MPI_TPOH_J1[16*9+15 : 16*9]        <= CPU_WDATA[15:0];
      8'hEA:  MPI_TPOH_J1[16*10+15 : 16*10]      <= CPU_WDATA[15:0];
      8'hEB:  MPI_TPOH_J1[16*11+15 : 16*11]      <= CPU_WDATA[15:0];
      8'hEC:  MPI_TPOH_J1[16*12+15 : 16*12]      <= CPU_WDATA[15:0];
      8'hED:  MPI_TPOH_J1[16*13+15 : 16*13]      <= CPU_WDATA[15:0];
      8'hEE:  MPI_TPOH_J1[16*14+15 : 16*14]      <= CPU_WDATA[15:0];
      8'hEF:  MPI_TPOH_J1[16*15+15 : 16*15]      <= CPU_WDATA[15:0];
      8'hF0:  MPI_TPOH_J1[16*16+15 : 16*16]      <= CPU_WDATA[15:0];
      8'hF1:  MPI_TPOH_J1[16*17+15 : 16*17]      <= CPU_WDATA[15:0];
      8'hF2:  MPI_TPOH_J1[16*18+15 : 16*18]      <= CPU_WDATA[15:0];
      8'hF3:  MPI_TPOH_J1[16*19+15 : 16*19]      <= CPU_WDATA[15:0];
      8'hF4:  MPI_TPOH_J1[16*20+15 : 16*20]      <= CPU_WDATA[15:0];
      8'hF5:  MPI_TPOH_J1[16*21+15 : 16*21]      <= CPU_WDATA[15:0];
      8'hF6:  MPI_TPOH_J1[16*22+15 : 16*22]      <= CPU_WDATA[15:0];
      8'hF7:  MPI_TPOH_J1[16*23+15 : 16*23]      <= CPU_WDATA[15:0];
      8'hF8:  MPI_TPOH_J1[16*24+15 : 16*24]      <= CPU_WDATA[15:0];
      8'hF9:  MPI_TPOH_J1[16*25+15 : 16*25]      <= CPU_WDATA[15:0];
      8'hFA:  MPI_TPOH_J1[16*26+15 : 16*26]      <= CPU_WDATA[15:0];
      8'hFB:  MPI_TPOH_J1[16*27+15 : 16*27]      <= CPU_WDATA[15:0];
      8'hFC:  MPI_TPOH_J1[16*28+15 : 16*28]      <= CPU_WDATA[15:0];
      8'hFD:  MPI_TPOH_J1[16*29+15 : 16*29]      <= CPU_WDATA[15:0];
      8'hFE:  MPI_TPOH_J1[16*30+15 : 16*30]      <= CPU_WDATA[15:0];
      8'hFF:  MPI_TPOH_J1[16*31+15 : 16*31]      <= CPU_WDATA[15:0];
      default: ;
      endcase
   end
end

always @(posedge RESET or posedge CPU_CLK) begin
   if ( RESET==1'b1 ) begin
      CPU_RDATA[15:0]                 <= 16'd0;
   end
   else if ( CPU_CS==1'b1 ) begin
      case ( CPU_ADDR[7:0] )
      8'hB2:  CPU_RDATA[15:0]         <= { 8'd0, MPI_TPOH_C2[7:0]};
      8'hB3:  CPU_RDATA[15:0]         <= { 8'd0, MPI_TPOH_G1[7:0]};
      8'hB4:  CPU_RDATA[15:0]         <= { 8'd0, MPI_TPOH_F2[7:0]};
      8'hB5:  CPU_RDATA[15:0]         <= { 8'd0, MPI_TPOH_H4[7:0]};
      8'hB6:  CPU_RDATA[15:0]         <= { 8'd0, MPI_TPOH_F3[7:0]};
      8'hB7:  CPU_RDATA[15:0]         <= { 8'd0, MPI_TPOH_K2[7:0]};
      8'hB8:  CPU_RDATA[15:0]         <= { 8'd0, MPI_TPOH_N1[7:0]};
      8'hBC:  CPU_RDATA[15:0]         <= { 12'd0,MPI_HDLC_LATENCY[3:0]};

      8'hE0:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*0+15 : 16*0];
      8'hE1:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*1+15 : 16*1];
      8'hE2:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*2+15 : 16*2];
      8'hE3:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*3+15 : 16*3];
      8'hE4:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*4+15 : 16*4];
      8'hE5:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*5+15 : 16*5];
      8'hE6:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*6+15 : 16*6];
      8'hE7:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*7+15 : 16*7];
      8'hE8:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*8+15 : 16*8];
      8'hE9:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*9+15 : 16*9];
      8'hEA:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*10+15 : 16*10];
      8'hEB:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*11+15 : 16*11];
      8'hEC:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*12+15 : 16*12];
      8'hED:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*13+15 : 16*13];
      8'hEE:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*14+15 : 16*14];
      8'hEF:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*15+15 : 16*15];
      8'hF0:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*16+15 : 16*16];
      8'hF1:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*17+15 : 16*17];
      8'hF2:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*18+15 : 16*18];
      8'hF3:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*19+15 : 16*19];
      8'hF4:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*20+15 : 16*20];
      8'hF5:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*21+15 : 16*21];
      8'hF6:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*22+15 : 16*22];
      8'hF7:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*23+15 : 16*23];
      8'hF8:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*24+15 : 16*24];
      8'hF9:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*25+15 : 16*25];
      8'hFA:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*26+15 : 16*26];
      8'hFB:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*27+15 : 16*27];
      8'hFC:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*28+15 : 16*28];
      8'hFD:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*29+15 : 16*29];
      8'hFE:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*30+15 : 16*30];
      8'hFF:  CPU_RDATA[15:0]         <= MPI_TPOH_J1[16*31+15 : 16*31];
      default:CPU_RDATA[15:0]         <= 16'd0 ;
      endcase
   end
end



endmodule 
